Publications

Found 23 results
Filters: First Letter Of Last Name is A and Author is Jaume Abella  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
A
M. Panic, Abella, J., Quinones, E., Hernandez, C., Ungerer, T., and Cazorla, F. J., “Analyzing TDMA and Round-Robin with MBPTA”, DSD 2015, 2015.
C
G. Fernandez, Abella, J., Quinones, E., Rochange, C., Vardanega, T., and Cazorla, F. J., “Contention in multicore hardware shared resources: Understanding of the state of the art”. WCET 2014 workshop, 2014.
E
M. Ziccardi, Mezzetti, E., Vardanega, T., Abella, J., and Cazorla, F. J., “EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis”, RTSS 2015, 2015.
J. Abella, del Castillo, J., Cazorla, F. J., and Padilla, M., “Extreme value theory in computer sciences: The case of embedded safety-critical systems”. 6th International Conference on Risk Analysis (ICRA), 2015.
F
L. Kosmidis, Quinones, E., Abella, J., Vardanega, T., Hernandez, C., Gianarro, A., Broster, I., and Cazorla, F. J., “Fitting Processor Architectures for Measurement-Based Probabilistic Timing Analysis”, 2016.
I
I. Agirre, Azkarate-askasua, M., Perez, J., Hernandez, C., Abella, J., Vardanega, T., and Cazorla, F. J., “IEC-61508 SIL3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis”, DSD 2015, 2015.
M
L. Kosmidis, Compagnin, D., Morales, D., Mezzetti, E., Quinones, E., Abella, J., Vardanega, T., and Cazorla, F. J., “Measurement-Based Timing Analysis of the AURIX Caches”. WCET 2016, 2016.
E. Diaz, Abella, J., Mezzetti, E., Agirre, I., Azkarate-askasua, M., Vardanega, T., and Cazorla, F. J., “Mitigating the Instrumentation Overhead of Measurement-Based Timing Analysis”. WCET 2016, 2016.
P. Benedicte, Kosmidis, L., Quinones, E., Abella, J., and Cazorla, F. J., “Modeling the Con dence of Timing Analysis for Time Randomised Caches”, SIES 2016, 2016.
P. Benedicte, Kosmidis, L., Quinones, E., Abella, J., and Cazorla, F. J., “Modeling the Confidence of Timing Analysis for Software Time Randomised Caches”, INDIN 2016, 2016.
S. Milutinovic, Abella, J., and Cazorla, F. J., “Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns”, ISORC 2016, 2016.
P
S. Milutinovic, Quinones, E., Abella, J., and Cazorla, F. J., “PACO: Fast Average-Performance Estimation for Time-Randomized Caches”, 52nd Design Automation Conference (DAC), 2015.
L. K. (BSC), Quinones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F. J., “Probabilistic Timing Analysis and Its Impact on Processor Architecture”, 2014.
F. J. Cazorla, Abella, J., Anderson, J., Vardanega, T., Vatrinet, F., Bate, I., Broster, I., Azkarate-askasua, M., Wartel, F., Cucu, L., Cros, F., Farrall, G., Gogonel, A., Gianarro, A., Triquet, B., and Hernand, C., “PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis”, DSD 2016, 2016.
M. Slijepcevic, Fernandez, M., Hernandez, C., Abella, J., Quinones, E., and Cazorla, F. J., “pTNoC: Time-Analyzable Scalable NoC Designs for Mixed-Criticality Multicore Embedded Systems”, DSD 2016, 2016.
R
E. Mezzetti, Ziccardi, M., Vardanega, T., Abella, J., Quinones, E., and Cazorla, F. J., “Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems”. Leibniz Transactions on Embedded Systems (LITES), 2015.
D. Trilla, Hernandez, C., Abella, J., and Cazorla, F. J., “Resilient Random Modulo Cache Memories for Probabilistically-Analyzable Real-Time Systems”, IOLTS 2016, 2016.
S
S. Milutinovic, Abella, J., Hardy, D., Quinones, E., Puaut, I., and Cazorla, F. J., “Speeding up Static Probabilistic Timing Analysis”, in ARCS, 2015.
T
L. Kosmidis, Vargas, R., Morales, D., Quinones, E., Abella, J., and Cazorla, F. J., “TASA: Toolchain-Agnostic Software Randomisation for Safety-Critical Real-Time Systems”, ICCAD 2016, 2016.
F. Wartel, Kosmidis, L., Gogonel, A., Baldovin, A., Stephenson, Z., Triquet, B., Quinones, E., Lo, C., Mezzetti, E., Broster, I., Abella, J., Cucu-Grosjean, L., Vardanega, T., and Cazorla, F. J., “Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms”, in DATE, 2015.
M. S. (BSC), (BSC), L. K., Abella, J., Quinones, E., and Cazorla, F., “Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments”, in Special Issue on Harsh Chips, 2014.
C. Hernandez, Abella, J., Cazorla, F. J., Andersson, J., and Gianarro, A., “Towards Making a LEON3 Multicore Compatible with Probabilistic Timing Analysis”, DASIA 2015, 2015.
W
J. Abella, Hernandez, C., Quinones, E., Cazorla, F. J., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., “WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness”, SIES 2015, 2015.